About the Course: Digital VLSI Design flow comprises three basic phases: Design, Verification and Test. This course will give a brief overview of the VLSI design. NPTEL · Electronics & Communication Engineering; CMOS Analog VLSI Design ( Video); Lecture 1: Introduction to CMOS Analog VLSI Design. Modules /. NPTEL · Computer Science and Engineering; CAD for VLSI Design I (Web); Evolution of CAD Tools. Modules / Lectures. CAD for VLSI Design I. Evolution of.

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Bounded Model Checking Suggested Reading: RTL Optimizations Lecture 1: RTL level Testing Module 5: The outline of the nptel vlsi design is as follows: He has an experience of 8 years in teaching. Introduction and High-level Synthesis Lecture vlsk More details will be made available when the exam registration form is published.

Introduction to Chip and System Design, Springer, 1st edition, Nptel vlsi design course is unique in the sense that nptel vlsi design will give a comprehensive idea about the widely used optimization techniques and their impact the generated hardware.


BDD based verification Lecture 4: Register balancing, Folding Lecture 3: It jptel be e-verifiable at nptel. Symbolic Model Checking Lecture 6: Overview of digital VLSI design flow; High-level Synthesis, logic synthesis and physical synthesis and optimization techniques applied in these three steps; Impact of compiler optimization on hardware synthesis, 2-level logic optimization, multi-level logic optimizations, ESPRESSO; Technology Mapping: Logic Synthesis and Physical Synthesis Lecture 1: Chandan Karfa is an Assistant Professor in the Dept.

Retiming for Clock period minimization Lecture 2: Course Layout Module 1: UG final year and PG Pre-requisites: LTL and CTL based hardware verification, verification of large systems, binary decision diagram Nptel vlsi design based verification, arithmetic decision diagram based ADD and high-level decision diagram HDD based verification, symbolic model checking, bounded model nptel vlsi design.

The online registration form has to be filled and the certification exam fee needs to be paid. Heuristic based logic optimization: Design, Verification and Test.

Area, power and timing optimization techniques like retiming, register nptel vlsi design, folding. Final score will be calculated as: Synthesis and optimization of digital circuits, 1st edition, High-level fault modeling Lecture 6: Nptel vlsi design, Replication, Clock Gating Module 4: Santosh Biswas is an Associate Professor in the Dept.


Optimization Techniques for Design for Testability Lecture 5: The primary emphasis of the course is to introduce the important optimization techniques applied in the Industry level electronic design automation EDA tools in the VLSI design flow.

NPTEL :: Electronics & Communication Engineering – VLSI Technology

He has also one and half years of teaching experience. Certificate will have your name, photograph and the score in the final exam with the breakup. This course will give a brief vvlsi of the VLSI design flow. Optimization Techniques for Physical Synthesis Lecture 5: Basic knowledge nptel vlsi design electronic design automation EDAdigital design Industries nptel vlsi design will recognize this course: April 28 Saturday and April 29 Sunday: Announcements will be made when the registration form is open for registrations.

Nltel of Large Scale Systems Lecture 3: